Fully Integrated WiFi6 Baseband Programmable Gain Amplifier (PGA) + Low-Pass Filter Design [Report]

  • March 2025 - May 2025 | Berkeley, CA
  • EE 240B Advanced Analog IC Design course taught by Prof. Osama Shana'a, IEEE Fellow, adjunct professor in UC Berkeley EECS, and Senior Director at MediaTek.
  • Developed a fully integrated PGA and lowpass filter targeting 10 MHz and 20 MHz WiFi6 baseband channel.
  • Full of 15 specifications, including 3dB-bandwidth, voltage gain (0dB-14dB), gain step (2dB), filter rejection, noise, linearity (P1dB, IM3), DC offset, settling time, shutdown leakage current, common-mode input/output voltage, and minimize power consumption.
  • Incorporated common-mode feedback for robust DC operating point.
  • Packaged using a 28-pin QFN. Assigned pin functions and designed the SPI interface.
  • All specs are met under nominal operating points, and most of them are met over PVT.

    • Design and Test of Synchronous Buck Converter for Photovoltaic (PV) Maximum Power Point Tracking (MPPT) [Report]

  • March 2025 - May 2025 | Berkeley, CA
  • EE 113B Power Electronics Design course taught by Prof. Jessica Boles, EECS, UC Berkeley
  • Designed and laid out a synchronous buck converter in Altium Designer for photovoltaic maximum power point tracking (MPPT) applications.
  • Built and validated a loss model including switching, conduction, winding, and core losses.
  • Sized components for ripple specs and hand-wound a custom inductor.
  • Assembled, debugged, and tested hardware across operating conditions.
  • Implemented a closed-loop MPPT algorithm (Perturb and Observe) using a TI C2000 microcontroller.

    • PCB

    Custom Designed MPPT Buck Converter PCB

    With Prof. Osama and friends

    Testbench Setup

    Analysis and Design of LCD Driver Amplifier

  • November 2024 - December 2024 | Berkeley, CA
  • EE 140 Analog Integrated Circuits course taught by Prof. Rikky Muller, EECS, UC Berkeley
  • Designed a two-stage (telescopic cascode & Class AB Amplifier) with high gain and high output swing.
  • Implemented in Cadence Virtuoso with a 45nm CMOS process.
  • Sizing transistors using the gm/ID methodology.

    • Implement the Tetris game on FPGA using the Verilog HDL programming language

  • November 2023 - January 2024 | Shenzhen, China
  • Digital Integrated Circuits course taught by Prof. Fengwei An, School of Microelectronics, SUSTech
  • Implement the Tetris game on an FPGA using Verilog, including features such as game start and pause, block falling, left/right movement, rotation, line clearing, and score display.
  • Modularize the testbench (including IP Core and PLL verification) and validate basic functionality through simulation.
  • Successfully validated key functionalities on the FPGA, ensuring system reliability.